An alternative carry-save arithmetic for new generation field programmable gate arrays
dc.authorid | cini, ugur/0000-0002-9827-7993 | |
dc.authorid | MORGUL, AVNI/0000-0002-7818-4706 | |
dc.authorwosid | Morgül, Avni/AAI-8159-2021 | |
dc.authorwosid | cini, ugur/AAT-6952-2020 | |
dc.contributor.author | Cini, Ugur | |
dc.contributor.author | Aktan, Mustafa | |
dc.contributor.author | Morgul, Avni | |
dc.date.accessioned | 2024-06-12T10:59:37Z | |
dc.date.available | 2024-06-12T10:59:37Z | |
dc.date.issued | 2016 | |
dc.department | Trakya Üniversitesi | en_US |
dc.description.abstract | In this work, a double carry-save addition operation is proposed, which is efficiently synthesized for 6-input LUT-based field programmable gate arrays (FPGAs). The proposed arithmetic operation is based on redundant number representation and provides carry propagation-free addition. Using the proposed arithmetic operation, a compact and fast multiply and accumulate unit is designed. To our knowledge, the proposed design provides the fastest multiply-add operation for 6-input LUT-based FPGA systems. A finite impulse response filter implementation is given to show the performance of the proposed structure. The proposed implementation provides a dramatic performance increase, which is at least 2 times faster than conventional binary multiply-add implementations. | en_US |
dc.identifier.doi | 10.3906/elk-1306-184 | |
dc.identifier.endpage | 447 | en_US |
dc.identifier.issn | 1300-0632 | |
dc.identifier.issn | 1303-6203 | |
dc.identifier.issue | 2 | en_US |
dc.identifier.scopus | 2-s2.0-84962608229 | en_US |
dc.identifier.scopusquality | Q3 | en_US |
dc.identifier.startpage | 435 | en_US |
dc.identifier.trdizinid | 244643 | en_US |
dc.identifier.uri | https://doi.org/10.3906/elk-1306-184 | |
dc.identifier.uri | https://search.trdizin.gov.tr/yayin/detay/244643 | |
dc.identifier.uri | https://hdl.handle.net/20.500.14551/20501 | |
dc.identifier.volume | 24 | en_US |
dc.identifier.wos | WOS:000369325300007 | en_US |
dc.identifier.wosquality | Q4 | en_US |
dc.indekslendigikaynak | Web of Science | en_US |
dc.indekslendigikaynak | Scopus | en_US |
dc.indekslendigikaynak | TR-Dizin | en_US |
dc.language.iso | en | en_US |
dc.publisher | Tubitak Scientific & Technological Research Council Turkey | en_US |
dc.relation.ispartof | Turkish Journal Of Electrical Engineering And Computer Sciences | en_US |
dc.relation.publicationcategory | Makale - Uluslararası Hakemli Dergi - Kurum Öğretim Elemanı | en_US |
dc.rights | info:eu-repo/semantics/openAccess | en_US |
dc.subject | Digital Arithmetic | en_US |
dc.subject | Redundant Numbers | en_US |
dc.subject | FPGA | en_US |
dc.subject | FIR Filters | en_US |
dc.title | An alternative carry-save arithmetic for new generation field programmable gate arrays | en_US |
dc.type | Article | en_US |