Cini, UgurAktan, MustafaMorgul, Avni2024-06-122024-06-1220161300-06321303-6203https://doi.org/10.3906/elk-1306-184https://search.trdizin.gov.tr/yayin/detay/244643https://hdl.handle.net/20.500.14551/20501In this work, a double carry-save addition operation is proposed, which is efficiently synthesized for 6-input LUT-based field programmable gate arrays (FPGAs). The proposed arithmetic operation is based on redundant number representation and provides carry propagation-free addition. Using the proposed arithmetic operation, a compact and fast multiply and accumulate unit is designed. To our knowledge, the proposed design provides the fastest multiply-add operation for 6-input LUT-based FPGA systems. A finite impulse response filter implementation is given to show the performance of the proposed structure. The proposed implementation provides a dramatic performance increase, which is at least 2 times faster than conventional binary multiply-add implementations.en10.3906/elk-1306-184info:eu-repo/semantics/openAccessDigital ArithmeticRedundant NumbersFPGAFIR FiltersArticle242435447Q4WOS:0003693253000072-s2.0-84962608229Q3244643