Erdem, OguzhanCarus, Aydin2024-06-122024-06-122013978-0-7695-5103-61550-4794https://doi.org/10.1109/HOTI.2013.11https://hdl.handle.net/20.500.14551/2511721st Annual IEEE Symposium on High-Performance Interconnects (HOTI) -- AUG 21-23, 2013 -- Cisco, San Jose, CAProviding a high operating frequency and abundant parallelism, Field Programmable Gate Arrays (FPGAs) are the most promising base to realize SRAM-based pipelined architectures for high-speed Internet Protocol (IP) lookup. Owing to the restrictions of the state-of-the-art FPGAs on the number of I/O pins and on-chip memory, the existing approaches can hardly accommodate the large and sparsely-distributed IPv6 routing tables. Therefore, memory efficient data structures are recently in high demand. In this paper, clustered linked list forest (CLLF) data structure is proposed for solving the longest prefix matching (LPM) problem in IP lookup. Our structure comprising clustered multiple parallel linked lists achieves significant memory compaction in comparison to the existing approaches. CLLF data structure is implemented on a high throughput SRAM-based parallel and pipelined architecture on FPGAs. Utilizing a state-of-the-art FPGA device, CLLF architecture can accommodate up to 712K IPv6 prefixes while supporting fast incremental routing table updates.en10.1109/HOTI.2013.11info:eu-repo/semantics/closedAccessIpv4/V6 LookupArchitectureTcamsConference Object3340N/AWOS:0003354055000052-s2.0-84889077345N/A