Cini, UgurKurt, Olcay2024-06-122024-06-122016978-1-5090-0336-5https://hdl.handle.net/20.500.14551/2224611th IEEE International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS) -- APR 12-14, 2016 -- Istanbul, TURKEYIn this work, carry-free redundant arithmetic based fused multiply-accumulate (MAC) units are designed. In the first design, a regular redundant carry-save MAC unit is designed using well known carry-save techniques. In the second design, a hybrid design is proposed to exploit fast carry chains of the FPGA together with double carry-save output encoding. The proposed scheme exploits fast-carry chains of the FPGA structure, and, multi-operand adders are divided into smaller blocks to increase the performance. The outputs of the multi-operand adders are not merged and the results are kept in double carry-save format where extra redundancy reduces critical path delay. Designed MAC units have 16x16-bit multiplier with 40-digit accumulate output for recursive multiply-add operations. The designs are synthesized on AlteraTM Stratix III FPGAs and provide superior performance compared to conventional pipelined carry-propagate multiply-accumulate units. The fusion in the arithmetic structure provides best performance compared to conventional pipelined multiplier based structures, hard multiplier based MAC units, and carry free redundant arithmetic based MAC structures as well.eninfo:eu-repo/semantics/closedAccessMAC UnitMulti-Operand AdderRedundant NumbersCarry-Save ArithmeticMatrix MultiplicationFIR FilteringFPGA ArithmeticConference ObjectN/AWOS:0003867567000182-s2.0-84978427215N/A