Cini, UgurKurt, Olcay2024-06-122024-06-122015978-1-5090-0246-7https://hdl.handle.net/20.500.14551/22247IEEE Conference on Electronics, Circuits, and Systems (ICECS) -- DEC 06-09, 2015 -- Cairo, EGYPTIn this work, an alternative redundant arithmetic based fused multiply-accumulate (MAC) unit is designed. The design utilizes double carry-save output encoding. The structure is especially suitable for 6-input LUT based reconfigurable systems. By employing only (6, 3) counters in the partial product reduction and accumulate operations, least amount of logic depth is provided which results as high performance without any pipeline in the system. The proposed system is not affected by carry propagation because of redundant arithmetic scheme implemented in the MAC structure. Designed MAC unit has 16x16-bit multiplier and 40-bit accumulate output. It is synthesized on Altera (TM) Stratix III FPGAs and provides better performance compared to conventional pipelined carry-propagate multiply-accumulate units.eninfo:eu-repo/semantics/closedAccessMAC UnitRedundant NumbersCarry-Save ArithmeticMatrix MultiplicationFIR FilteringFPGA ArithmeticConference Object649652N/AWOS:000380571000163