Soylu, TuncayErdem, OguzhanCarus, Aydin2024-06-122024-06-1220201389-12861872-7069https://doi.org/10.1016/j.comnet.2019.106977https://hdl.handle.net/20.500.14551/24366Traffic classification is the determination of the application types during real-time flow of internet traffic. Machine learning (ML) based classification approaches that can classify internet traffic using statistical properties of flows are of great interest, due to its ability to work under encrypted traffic conditions. In this paper, we propose a novel data structure, named Bit Vector Coded Simple CART (BC-SC), for ML based internet traffic classification. BC-SC data structure is a scalable solution in terms of the number of application classes while providing a significant improvement in search latency, memory requirement and throughput when compared to the state-of-the-art approaches. We also designed two alternative hardware architectures, namely Pipelined and Discrete Parallel Range Comparators (DPRC)-based, on the Field Programmable Gate Array (FPGA) platform to support BC-SC data structure. Pipelined and DPRC-based architectures can achieve up to 665 and 914 giga bit per second (Gbps) or 2078 and 2857 million classifications per second (MCPS) respectively for the minimum packet size of 40 Byte. Furthermore, the proposed engines both can reach 96.8125% accuracy with eight application classes. (C) 2019 Elsevier B.V. All rights reserved.en10.1016/j.comnet.2019.106977info:eu-repo/semantics/closedAccessTraffic ClassificationMachine LearningSimple CARTHigh ThroughputLow LatencyFPGAData StructureNetworksBit vector-coded simple CART structure for low latency traffic classification on FPGAsArticle167Q1WOS:0005105246000082-s2.0-85075313928Q1