An efficient partitioning and placement based fault TSV detection in 3D-IC using deep learning approach
Küçük Resim Yok
Tarih
2021
Dergi Başlığı
Dergi ISSN
Cilt Başlığı
Yayıncı
Springer Heidelberg
Erişim Hakkı
info:eu-repo/semantics/closedAccess
Özet
Over topical eras, three dimensional Integrated Circuit (3D-IC) fabrications have become vital among the researchers and industrial people, owing to its wide range of amenities including smaller intersect lengths, advanced incorporation density, and enhanced performance. Still, fault Through Silicon Via (TSV) detection is a bottleneck, due to poor fabrication processes such as partitioning and placement. Besides, state of the art works have concentrated on redundant TSV allocation instead of detected fault TSV and hence, the area overhead and size of the circuit are increased. To resolve these shortcomings, this paper proposes an Efficient Partitioning and Placement based Fault TSV detection in 3D-IC. The proposed work comprises five processes: Quick cut oriented Partitioning, Multi-Objective based Placement, Deep learning based Fault TSV detection, Re-routing and Adaptive Time Division Multiple Access (TDMA) time slot. Initially, Quick Cut algorithm has been employed to partition the 3D-IC and it is easier for placement process. The placement is executed through Multi-Objective Brain Storm Optimization algorithm that selects the optimal place to position the cells in 3D-IC. The fault TSV in the 3D-IC is detected using the Adam Deep Neural Network algorithm. Further, Adam optimizer has been used to estimate weight for each input and it provides fast performance and better convergence rate compared to the traditional stochastic gradient algorithm. After obtaining the fault TSV, rerouting is performed to reroute the signals transmitted over the defected TSV to the nearby defect free TSV. The Adaptive TDMA algorithm has been used to provide time slot to TSV positioned in each partition. The proposed method has been implemented in MATLABR2017b tool. The results attained from the simulations are propitious in terms of the metrics such as Area, Wirelength, Delay, Run time and Temperature.
Açıklama
Anahtar Kelimeler
Three Dimensional Integrated Circuit, Quick Cut, Placement, Fault Through Silicon Via, Re-Routing, Adaptive Time Slot
Kaynak
Journal Of Ambient Intelligence And Humanized Computing
WoS Q Değeri
Q2
Scopus Q Değeri
Q1
