MAC Unit for Reconfigurable Systems Using Multi-Operand Adders with Double Carry-Save Encoding

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dc.authoridcini, ugur/0000-0002-9827-7993
dc.authorwosidcini, ugur/AAT-6952-2020
dc.contributor.authorCini, Ugur
dc.contributor.authorKurt, Olcay
dc.date.accessioned2024-06-12T11:07:56Z
dc.date.available2024-06-12T11:07:56Z
dc.date.issued2016
dc.departmentTrakya Üniversitesien_US
dc.description11th IEEE International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS) -- APR 12-14, 2016 -- Istanbul, TURKEYen_US
dc.description.abstractIn this work, carry-free redundant arithmetic based fused multiply-accumulate (MAC) units are designed. In the first design, a regular redundant carry-save MAC unit is designed using well known carry-save techniques. In the second design, a hybrid design is proposed to exploit fast carry chains of the FPGA together with double carry-save output encoding. The proposed scheme exploits fast-carry chains of the FPGA structure, and, multi-operand adders are divided into smaller blocks to increase the performance. The outputs of the multi-operand adders are not merged and the results are kept in double carry-save format where extra redundancy reduces critical path delay. Designed MAC units have 16x16-bit multiplier with 40-digit accumulate output for recursive multiply-add operations. The designs are synthesized on AlteraTM Stratix III FPGAs and provide superior performance compared to conventional pipelined carry-propagate multiply-accumulate units. The fusion in the arithmetic structure provides best performance compared to conventional pipelined multiplier based structures, hard multiplier based MAC units, and carry free redundant arithmetic based MAC structures as well.en_US
dc.description.sponsorshipBahcesehir Univ,Hacettepe Univ,Politecnico Torino,ENIS,Consorzio Interuniversitario Nazl lInformatica,LIRMM,IEEE,IEEE Council Elect Design Automaten_US
dc.identifier.isbn978-1-5090-0336-5
dc.identifier.scopus2-s2.0-84978427215en_US
dc.identifier.scopusqualityN/Aen_US
dc.identifier.urihttps://hdl.handle.net/20.500.14551/22246
dc.identifier.wosWOS:000386756700018en_US
dc.identifier.wosqualityN/Aen_US
dc.indekslendigikaynakWeb of Scienceen_US
dc.indekslendigikaynakScopusen_US
dc.language.isoenen_US
dc.publisherIEEEen_US
dc.relation.ispartof2016 11th Ieee International Conference On Design & Technology Of Integrated Systems In Nanoscale Era (Dtis)en_US
dc.relation.publicationcategoryKonferans Öğesi - Uluslararası - Kurum Öğretim Elemanıen_US
dc.rightsinfo:eu-repo/semantics/closedAccessen_US
dc.subjectMAC Uniten_US
dc.subjectMulti-Operand Adderen_US
dc.subjectRedundant Numbersen_US
dc.subjectCarry-Save Arithmeticen_US
dc.subjectMatrix Multiplicationen_US
dc.subjectFIR Filteringen_US
dc.subjectFPGA Arithmeticen_US
dc.titleMAC Unit for Reconfigurable Systems Using Multi-Operand Adders with Double Carry-Save Encodingen_US
dc.typeConference Objecten_US

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