A MAC Unit with Double Carry-Save Scheme Suitable for 6-Input LUT Based Reconfigurable Systems
Küçük Resim Yok
Tarih
2015
Yazarlar
Dergi Başlığı
Dergi ISSN
Cilt Başlığı
Yayıncı
IEEE
Erişim Hakkı
info:eu-repo/semantics/closedAccess
Özet
In this work, an alternative redundant arithmetic based fused multiply-accumulate (MAC) unit is designed. The design utilizes double carry-save output encoding. The structure is especially suitable for 6-input LUT based reconfigurable systems. By employing only (6, 3) counters in the partial product reduction and accumulate operations, least amount of logic depth is provided which results as high performance without any pipeline in the system. The proposed system is not affected by carry propagation because of redundant arithmetic scheme implemented in the MAC structure. Designed MAC unit has 16x16-bit multiplier and 40-bit accumulate output. It is synthesized on Altera (TM) Stratix III FPGAs and provides better performance compared to conventional pipelined carry-propagate multiply-accumulate units.
Açıklama
IEEE Conference on Electronics, Circuits, and Systems (ICECS) -- DEC 06-09, 2015 -- Cairo, EGYPT
Anahtar Kelimeler
MAC Unit, Redundant Numbers, Carry-Save Arithmetic, Matrix Multiplication, FIR Filtering, FPGA Arithmetic
Kaynak
2015 Ieee Conference On Electronics, Circuits, And Systems (Icecs)
WoS Q Değeri
N/A
