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Öğe Efficiency and power density optimization of three-level tp pfc(Mesago PCIM GmbH, 2021) Bulut E.B.; Gulbahce M.O.; Kocabas D.A.; Dusmez S.Si based three-level (3L) totem-pole (TP) Power Factor Correction (PFC) topology is a low cost alternative to two-level TP PFC with wide-band gap devices providing high power density and high efficiency. This study proposes a system level optimization algorithm through modeling all sub-systems of the converter including differential mode noise filter, PFC inductor, heatsink required by the FETs. Depending on the weights assigned between volume, cost and power loss, the algorithm chooses the switching frequency, designs the PFC inductor, and chooses the FETs from the database that minimizes the given cost function. In this study, a 3.7 kW 3L TP PFC is designed with a final cost function having 60%, 20% and 20% weighting coefficients for volume, cost and power loss, respectively. Results show that optimum design reached 99.01% of efficiency, with total volume of 340 cm3 for DM filter, PFC inductor, heatsink and bus capacitor. © VDE VERLAG GMBH · Berlin · Offenbach.Öğe Simplified method to analyze drive strengths for gan power devices(Mesago PCIM GmbH, 2021) Bulut E.B.; Gulbahce M.O.; Kocabas D.A.; Dusmez S.GaN power switches enable ultra-fast switching speeds, yet, the maximum gate drive strength is mainly limited by the voltage overshoot across drain-source junction. There is a complex relationship between the power loop inductance, gate resistance, load current, parasitic capacitances of the GaN FET and the resultant voltage ringing. In this paper, a simplified method to relate the gate drive strength with the voltage overshoot is presented. With this approach, it is possible to find a maximum achievable dV/dt for different GaN FETs as well as various board and package parasitics under different operating conditions, which helps designers to identify and compare I-V overlap losses of various GaN FETs without running SPICE models. © VDE VERLAG GMBH · Berlin · Offenbach.